In this paper, an ultra-low-power low-noise amplifier (LNA) at 5GHz is proposed. The main focus is on precise computation of output impedance, input impedance, and gain of the LNA. The LNA is composed of a common-source LNA and a cascode LNA. In fact, the casode LNA can assist to have more stability by declining S12 considerably. Plus, it can be beneficial via increasing the gain of the second stage of the final LNA. In addition, in order to emphasize the significance of the meticulous calculations, the formulas calculated in this paper are compared with their counterparts in other papers. The combination of two different supply voltage is mentioned as an approach to bring down the power dissipation of the circuit. Simulation is performed by MATLAB, HSPICE, and Advanced Design System (ADS). TSMC 0.18 um CMOS process is used to evaluate the circuit. The LNA is analyzed with two different voltage supply 0.7 V and 0.9 V. The input matching (S11) is -14 dB and -16 dB for voltage supply 0.7 V and 0.9 V respectively. Plus, power dissipation, noise figure (NF), and gain (S21) are 532 μW, 944 μW, 1.25 dB, 1.05dB, 15dB, and 17dB for voltage supply 0.7 V and 0.9 V respectively.
Published in | American Journal of Networks and Communications (Volume 8, Issue 1) |
DOI | 10.11648/j.ajnc.20190801.11 |
Page(s) | 1-17 |
Creative Commons |
This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited. |
Copyright |
Copyright © The Author(s), 2019. Published by Science Publishing Group |
Cascode, Common Source, Precise Calculation, Ultra-Low-Power, Low Noise
[1] | Fakharzadeh, M., M. R. Nezhad-Ahmadi, B. Biglarbegian, J. Ahmadi-Shokouh, and S. Safavi-Naeini, “CMOS phased array transceiver technology for 60GHz wireless applications,” IEEETransactions on Antennas and Propagation, Vol. 58, 1093–1104, Apr. 2010. |
[2] | Bozzola, S., D. Guermandi, F. Vecchi, M. Repossi, M. Pozzoni, A. Mazzanti, and F. Svelto, “A sliding IF receiver for mm-wave WLANs in 65 nm CMOS,” IEEE CICC’09, 669–672, 2009. |
[3] | Parsa, A. and B. Razavi, “A 60 GHz CMOS receiver using a 30 GHz LO,” ISSCC’08, 190–606, 2008. |
[4] | Yu, Y. K., P. G. M. Baltus, A. de Graauw, E. van der Heijden, C. S. Vaucher, and A. H. M. van Roermund, “A 60GHz phase shifter integrated with LNA and PA in 65 nm CMOS for phased array systems,” IEEE Journal of Solid-State Circuits, Vol. 45, 1697–1709, Sept. 2010. |
[5] | Fritsche, D., G. Tretter, C. Carta, and F. Ellinger, “Millimeter-wave low-noise amplifier design in 28-nm low-power digital CMOS,” IEEE Transactions on Microwave Theory and Techniques, Vol. 63, 1910–1922, 2015. |
[6] | Arbabian, A. and A. M. Niknejad, “Design of a CMOS tapered cascaded multistage distributed amplifier,” IEEE Transactions on Microwave Theory and Techniques, Vol. 57, 938–947, Apr. 2009. |
[7] | Guo, B., J. Chen, L. Li, H. Jin, and G. Yang, “A wideband noise-canceling CMOS LNA with enhanced linearity by using complementary nMOS and pMOS configurations,” IEEE Journal of Solid-State Circuits, Vol. 52, 1331–1344, May 2017. |
[8] | Pan, Z., C. Qin, Z. Ye, and Y. Wang, “A low power inductorless wideband LNA with Gm enhancement and noise cancellation,” IEEE Microwave and Wireless Components Letters, Vol. 27, 58–60, 2017. |
[9] | Kuo, M.-C., C.-N. Kuo, and T.-C. Chueh, “Wideband LNA compatible for differential and singleended inputs,” IEEE Microwave and Wireless Components Letters, Vol. 19, 482–484, Jul. 2009. |
[10] | Kim, S. J., D. Lee, K. Y. Lee, and S. G. Lee, “A 2.4-GHz super-regenerative transceiver with selectivity-improving dual Q-enhancement architecture and 102-μW all-digital FLL,” IEEE Transactions on Microwave Theory and Techniques, Vol. 65, 3287–3298, Sep. 2017. |
[11] | CIMINO, M., LAPUYADE, H., DEVAL, Y. et al. Design of a 0.9 V 2.45 GHz self-testable and reliability-enhanced CMOS LNA. IEEE Journal of Solid-State Circuits, 2008, vol. 43, no. 5, p. 1187 - 1194. |
[12] | Chen, K. H., J. H. Lu, B. J. Chen, and S. L. Liu, \An ultra-wide- band 0.4{10 GHz LNA in 0.18 ¹m CMOS," IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 54, No. 3, 217{221, Mar. 2007. |
[13] | Lai, M. T. and H. W. Tsao, “Ultra-low-power cascaded CMOS LNA with positive feedback and bias optimization,” IEEE Transactions on Microwave Theory and Techniques, Vol. 61, 1934–1945, 2013. |
[14] | G. Gonzalez, Microwave Transistor Amplifiers: Analysis and Design, 2nd ed. Upper Saddle River. Englewood Cliffs, NJ, USA: Prentice- Hall, 1997. |
[15] | D. Linten, S. Thijs, M. I. Natarajan, P. Wambacq, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Donnay, and S. Decoutere, “A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1434–1442, Jul. 2005. |
[16] | R. Brederlow, W. Weber, J. Sauerer, S. Donnay, P. Wambacq, and M. Vertregt, “A mixed signal design roadmap,” IEEE Design Test Comput., vol. 18, no. 6, pp. 34–46, Nov.–Dec. 2001. |
[17] | W. Jeamsaksiri, A. Mercha, J. Ramos, D. Linten, S. Thijs, S. Jenei, C. Detcheverry, P. Wambacq, R. Velghe, and S. Decoutere, “Integration of a 90 nm RF CMOS technology (200 GHz fmax—150 GHz fT NMOS) demonstrated on a 5 GHz LNA,” in IEEE Symp. VLSI Technology Dig. Tech. Papers, Jun. 2004, pp. 100–101. |
[18] | D. Linten, L. Aspemyr, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Thijs, R. Garcia, H. Jacobsson, P. Wambacq, S. Donnay, and S. Decoutere, “Low-power 5 GHz LNA and VCO in 90 nm RF CMOS,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2004, pp. 372–375. |
[19] | P. Leroux and M. Steyaert, “A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBM,” in Proc Eur. Solid- State Circuits Conf., Sep. 2004, pp. 295–298. |
[20] | T. K. K. Tsang and M. El-Gamal, “Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNA,” in Proc. ISCAS, vol. 4, May 2002, pp. 795–798. |
[21] | H. W. Chiu and S. S. Lu, “A 2.17 dB NF, 5 GHz band monolithic CMOS LNA with 10 mW DC power consumption,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2002, pp. 226–229. |
[22] | E. H. Westerwick, “A 5 GHz band low noise amplifier with a 2.5 dB noise figure,” in Proc. IEEE Int. Symp. VLSI Technology, Systems, and Application, Apr. 2001, pp. 224–227. |
[23] | D. Mukherjee, J. Bhattacharjee, S. Chakaraborty, and J. Laskar, “A 5–6 GHz fully integrated CMOS LNA for a dual-band WLAN receiver,” in Proc. IEEE RAWCON, Sep. 2002, pp. 213–215. |
[24] | S. Asgaran, M. J. Deen, and C.-H. Chen, “A 4-mW monolithic CMOS LNA at 5.7 GHZ with the gate resistance used for input matching,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 4, pp. 188–190, Apr. 2006. |
[25] | Y. S. Wang and L. H. Lu, “5.7 GHZ low-power variable-gain LNA in 0.18 m CMOS,” Electron. Lett., vol. 41, pp. 66–68, 2005. |
[26] | D.-K. Wu, R. Huang, W. Wong, and Y. Wang, “A 0.4-V low noise amplifier using forward body bias technology for 5 GHZ application,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 7, pp. 543–545, Jul. 2007. |
[27] | D. Linten, S. Thijs, M. I. Natarajan, P. Wambacq, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Donnay, and S. Decoutere, “A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1434–1442, Jul. 2005. |
[28] | D. Linten, L. Aspemyr, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Thijs, R. Garcia, H. Jacobsson, P. Wambacq, S. Donnay, and S. Decoutere, “Low-power 5 GHZ LNA and vco in 90 nm RF CMOS,” in Proc. IEEE VLSI Circuits Symp., Jun. 2004, pp. 372–375. |
[29] | H.-H. Hsieh and L.-H. Lu, “Design of ultra-low-voltage RF front ends with complementary current-reused architectures,” IEEE Trans. Microw. Theory Techn., vol. 55, no. 7, pp. 1445–1458, Jul. 2007. |
[30] | H.-H. Hsieh, J.-H. Wang, and L.-H. Lu, “Gain-enhancement techniques for CMOS folded cascode LNAs at low-voltage operations,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 8, pp. 1807–1816, Aug. 2008. |
[31] | K. Han, J. Gil, S.-S. Song, J. Han, H. Shin, C. K. Kim, and K. Lee, “Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier,” IEEE J. Solid- State Circuits, vol. 40, no. 3, pp. 726–735, Mar. 2005. |
[32] | X. Li, S. Shekhar, and D. J. Allstot, “ -boosted common-gate LNA and differential Colpitts VCO/QVCO in 0.18 m CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2609–2619, Dec. 2005. |
[33] | J. S. Walling, S. Shekhar, andD. J. Allstot, “A -boosted currentreuse LNA in 0.18 m CMOS,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2007, pp. 613–616. |
[34] | G. Sapone and G. Palmisano, “A 3–10-GHz low-power CMOS lownoise amplifier for ultra-wideband communication,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 3, pp. 678–686, Mar. 2011. |
[35] | X. Yu and N. M. Neihart, “Analysis and design of a reconfigurable multimode low-noise amplifier utilizing a multitap transformer,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 3, pp. 1236–1246, Mar. 2013. |
[36] | A. Madan, M. J. McPartlin, C. Masse, W. Vaillancourt, and J. D. Cressler, “A 5 GHZ 0.95 dB NF highly linear cascode floating-body LNA in 180 nm soi CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 22, no. 4, pp. 200–202, Apr. 2012. |
APA Style
Hemad Heidari Jobaneh. (2019). An Ultra-Low-Power 5 GHz LNA Design with Precise Calculation. American Journal of Networks and Communications, 8(1), 1-17. https://doi.org/10.11648/j.ajnc.20190801.11
ACS Style
Hemad Heidari Jobaneh. An Ultra-Low-Power 5 GHz LNA Design with Precise Calculation. Am. J. Netw. Commun. 2019, 8(1), 1-17. doi: 10.11648/j.ajnc.20190801.11
AMA Style
Hemad Heidari Jobaneh. An Ultra-Low-Power 5 GHz LNA Design with Precise Calculation. Am J Netw Commun. 2019;8(1):1-17. doi: 10.11648/j.ajnc.20190801.11
@article{10.11648/j.ajnc.20190801.11, author = {Hemad Heidari Jobaneh}, title = {An Ultra-Low-Power 5 GHz LNA Design with Precise Calculation}, journal = {American Journal of Networks and Communications}, volume = {8}, number = {1}, pages = {1-17}, doi = {10.11648/j.ajnc.20190801.11}, url = {https://doi.org/10.11648/j.ajnc.20190801.11}, eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.ajnc.20190801.11}, abstract = {In this paper, an ultra-low-power low-noise amplifier (LNA) at 5GHz is proposed. The main focus is on precise computation of output impedance, input impedance, and gain of the LNA. The LNA is composed of a common-source LNA and a cascode LNA. In fact, the casode LNA can assist to have more stability by declining S12 considerably. Plus, it can be beneficial via increasing the gain of the second stage of the final LNA. In addition, in order to emphasize the significance of the meticulous calculations, the formulas calculated in this paper are compared with their counterparts in other papers. The combination of two different supply voltage is mentioned as an approach to bring down the power dissipation of the circuit. Simulation is performed by MATLAB, HSPICE, and Advanced Design System (ADS). TSMC 0.18 um CMOS process is used to evaluate the circuit. The LNA is analyzed with two different voltage supply 0.7 V and 0.9 V. The input matching (S11) is -14 dB and -16 dB for voltage supply 0.7 V and 0.9 V respectively. Plus, power dissipation, noise figure (NF), and gain (S21) are 532 μW, 944 μW, 1.25 dB, 1.05dB, 15dB, and 17dB for voltage supply 0.7 V and 0.9 V respectively.}, year = {2019} }
TY - JOUR T1 - An Ultra-Low-Power 5 GHz LNA Design with Precise Calculation AU - Hemad Heidari Jobaneh Y1 - 2019/06/29 PY - 2019 N1 - https://doi.org/10.11648/j.ajnc.20190801.11 DO - 10.11648/j.ajnc.20190801.11 T2 - American Journal of Networks and Communications JF - American Journal of Networks and Communications JO - American Journal of Networks and Communications SP - 1 EP - 17 PB - Science Publishing Group SN - 2326-8964 UR - https://doi.org/10.11648/j.ajnc.20190801.11 AB - In this paper, an ultra-low-power low-noise amplifier (LNA) at 5GHz is proposed. The main focus is on precise computation of output impedance, input impedance, and gain of the LNA. The LNA is composed of a common-source LNA and a cascode LNA. In fact, the casode LNA can assist to have more stability by declining S12 considerably. Plus, it can be beneficial via increasing the gain of the second stage of the final LNA. In addition, in order to emphasize the significance of the meticulous calculations, the formulas calculated in this paper are compared with their counterparts in other papers. The combination of two different supply voltage is mentioned as an approach to bring down the power dissipation of the circuit. Simulation is performed by MATLAB, HSPICE, and Advanced Design System (ADS). TSMC 0.18 um CMOS process is used to evaluate the circuit. The LNA is analyzed with two different voltage supply 0.7 V and 0.9 V. The input matching (S11) is -14 dB and -16 dB for voltage supply 0.7 V and 0.9 V respectively. Plus, power dissipation, noise figure (NF), and gain (S21) are 532 μW, 944 μW, 1.25 dB, 1.05dB, 15dB, and 17dB for voltage supply 0.7 V and 0.9 V respectively. VL - 8 IS - 1 ER -